Statistical Analysis of Digital ICs

Multi billion dollar semiconductor companies like intel and IBM try to increase the speed and decrease the power and the size of their chips. For this purpose, they always try to use smaller and smaller transistors where smaller transistors mean more functional chips with higher speeds. For instance, Intel processors had started with 10 um (micro meter) transistors in 1971 for manufacturing Intel 4004. Intel 4004 had only 2300 transistors and its speed was 108 KHz. By 2007, only after about 35 years, the transistor sizes had become 45 nm (nanometer), which was used to manufacture Intel Core2 Extreme processors. The number of transistors in these processors were more than 820,000,000 and the speed of the processors was more than 3 GHz.

However, decreasing the transistor sizes to produce digital ICs (Integrated Circuits or chips) with smaller area and higher speeds has led up to many problems. Now the chip manufacturing process is prone to errors and variations. The statistical variations of the transistor and circuit parameters result in many chips thrown away after manufacturing as they can not satisfy the timing requirements. As a result, it became an obligation to consider the statistical variations of digital circuits in stages before manufacturing and perform statistical timing analysis to estimate timing yield before manufacturing.

Today, many companies like Intel, IBM, Cadence, Synopsis, Mentor; many Computer Aided Design (CAD) research groups in academic institutions like Berkeley, MIT, Carnegie Mellon try to develop a statistical timing analysis tool that can estimate timing yield accurately and efficiently.

We also work on this topic and develop accurate and efficient statistical timing analysis tools to estimate timing yield of digital circuits. MS candidates eager to work on this topic are welcome. For further information please check the following papers:

The History of Intel Processor Technology

Why are Timing Estimates so Uncertain?

Statistical Timing Analysis Survey

Fast Monte Carlo Estimation of Timing Yield


Hardware Security

The integrate circuit design and manufacturing are prone to insertions at almost all stages. The undesired insertions to the circuit may cause in malfunctioning, information leakage or performance degradation. These insertions are are called hardware trojan horses (HTH) and are very difficult to be detected. The results are even more disastrous when national defence industry is considered.

The incredible costs of having national IC manufacturing facility, the complexity of the digital circuits, hiding of the HTHs until a specific rare input sequence comes, the unavoidable parameter variations and the possibility of insertion at each of many different design and manufacturing stages make the problem even worse. The topic has been included by some top conferences like DAC and extensive effort has been expended especially for the last years. There are destructive methods, which includes the cutting of the IC into its layers and reverse engineering for detecting the HTHs. The destructive methods are very difficult to applyi require sophisticated tools and time consuming. Also the circuits without HTHs can be used no more after destructive methods are applied. On the other hand non destructive methods have to solve many problems like the noise effect of parameter variations which mask the HTHs. Also most of the non destructive methods have to assume golden chips, which are somehow known to have no HTHs. As a result, detection of HTHs is an essential research area with many unsolved problems waiting to be solved.


e-mail: bayrakci@bilmuh.gyte.edu.tr




Nvidia Geforce 8800 die and its corresponding wafer



Circuit Delay variation increases with smaller transistors


Taken from "A Survey of Hardware Trojan Taxonomy and Detection" Tehranipor et. al.
From "A Survey of Hardware Trojan Taxonomy and Detection" Tehranipoor et. al.